1. Field of the Invention
The present invention relates to a semiconductor package such as a ball grid array (BGA) type semiconductor package which includes a wiring board, a semiconductor device mounted on a top surface of the wiring board, a seating resin layer formed on the top surface of the wiring board so as to seal and protect the semiconductor device, and a plurality of external electrode terminals such as solder balls provided on a bottom surface of the wiring board.
2. Description of the Related Art
Conventionally, a semiconductor device used in a BGA type semiconductor package includes a rectangular-silicon substrate derived from a monocrystalline silicon wafer, an insulating underlayer or contact layer formed on a top surface of the silicon substrate, and a multi-layered-insulating structure formed on the contact layer.
The multi-layered insulating structure includes a plurality of insulating interlayers stacked in order, and both a plurality of conductive pattern layers and a plurality of via-structures are alternately formed in the insulating interlayers so that the conductive pattern layers are electrically connected to each other through the via-structures.
Conventionally, each of the insulating interlayers is formed as a silicon dioxide layer, and the conductive pattern layers and the via-structures are composed of aluminum.
With the recent advance of miniaturization and integration of semiconductor devices such as 130 nm node semiconductor devices, multi-layered insulating structures become smaller, and thus the conductive pattern layers for signal transmission become thinner, resulting in delay of signal propagation in the conductive patterns, due to parasitic resistance of the transmission conductive pattern layers and parasitic capacitance involved in the conductive pattern layers.
In short, the miniaturization of semiconductor devices has advanced to a degree in which a magnitude of a dielectric constant of the silicon dioxide layer and a magnitude of a resistance of the aluminum conductive pattern layers cannot be neglected.
Thus, there is a recent trend toward use of copper, exhibiting a smaller specific resistance than that of aluminum, for the conductive patterns, whereby it is possible to facilitate the signal transmission in the conductive pattern layers. Also, it has been proposed that an insulating interlayer, composed of a low-k material having a smaller dielectric constant than that of silicon dioxide, be substituted for the silicon dioxide layer, to thereby suppress the production of the parasitic capacitance. Note, for the low-k material, SiOC, SiC, SiOF, porous SiO2, porous SiOC or the like may be used.
Nevertheless, the low-k insulating interlayer has an inferior physical strength to that of the silicon dioxide layer. Thus, the low-k insulating interlayer is susceptible to defects such as cracks during various processes for manufacturing the semiconductor device.
Also, the conductive pattern layers are liable to be peeled from the low-k insulating interlayers due to the fact that the difference in a thermal expansion coefficient between the low-k insulating interlayers and the conductive pattern layers is relatively large.
Further, the low-k insulating interlayers tend to absorb moisture, and the absorbed moisture causes corrosion in the conductive pattern layers in the multi-layered insulating structure.
In JP-2002-141474 A, it has been proposed that an endless rectangular guard-ring resistance circuit is formed in the multi-layered insulating structure along the periphery thereof, and is provided with four probing electrode pads exposed on a top surface of the multi-layered insulating structure and arranged at the corners of the top surface thereof. The guard ring resistance circuit is utilized to determine whether defects and/or peeling occur in the interior of the multi-layered insulating structure.
In particular, a resistance is measured between the probing electrode pad, and the measured resistance value is compared with a normal resistance value. When defects and/or peeling have occurred in the guard-ring resistance circuit, the measured resistance value differs from the normal resistance value. Thus, when the measured resistance value differs from the normal resistance value, it is possible to presume that defects and/or peeling have occurred in the interior of the multi-layered insulating structure. Note that this will be explained later in detail.
Also, in JP-2002-093918 A, it has been proposed that three ring-like open resistance circuits are formed in the multi-layered insulating structure along the periphery thereof, and each of the ring-like open resistance circuits terminates with a pair of electrode terminals adjacent to each other. The ring-like open resistance circuits are utilized to determine whether defects and/or peeling occur in the interior of the multi-layered insulating structure.
In particular, in each of the ring-like open resistance circuits, a resistance is measured between the two adjacent electrode terminals, and the measured resistance value is compared with a normal resistance value. When defects and/or peeling have occurred in the corresponding ring-like open resistance circuit, the measured resistance value differs from the normal resistance value. Thus, when the measured resistance value differs from the normal resistance value, it is possible to presume that defects and/or peeling have occurred in the interior of the multi-layered insulating structure.
In JP-2002-093918 A, when a crack occurs as a defect in a space between the two adjacent electrode terminals of each of the ring-like open resistance circuits, the crack cannot be detected by the measurement of the resistance value between the adjacent electrode terminals. This problem can be solved by forming more than three ring-like open resistance circuits in the multi-layered insulating structure such that the pairs of electrode terminals are shifted from each other along the periphery thereof, but an area for forming the more than three ring-like open resistance circuits is increased so that an area for forming the conductive pattern layers is restricted in the multi-layered insulating structure. Note that this will be explained later in detail.